Analogue in-memory computing for accelerating massive MIMO processing in 6G
Piergiulio Mannocci a, Enrico Melacarne a, Daniele Ielmini a
a Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano and IU.NET, Piazza L. da Vinci 32, 20133, Milano, Italy
Proceedings of Neuromorphic Materials, Devices, Circuits and Systems (NeuMatDeCaS)
VALÈNCIA, Spain, 2023 January 23rd - 25th
Organizers: Rohit Abraham John, Irem Boybat, Jason Eshraghian and Simone Fabiano
Contributed talk, Piergiulio Mannocci, presentation 041
DOI: https://doi.org/10.29363/nanoge.neumatdecas.2023.041
Publication date: 9th January 2023

In-memory computing (IMC) has gained traction as the leading candidate for the next computational architecture, overcoming the limitations of the classical von-Neumann computing machines by performing computation directly within the memory unit. Coupled with crosspoint arrays of resistive memories, IMC has potential for unprecedentedly high throughput and energy efficiency [1], by exploiting Kirchhoff and Ohm’s law in an open-loop fashion to perform matrix-vector multiplication (MVM). To alleviate the dependence of open-loop IMC on external digital signal processors, closed-loop, analogue feedback-based structures have been proposed, enabling one-step linear system solution [2] and linear regression [3]. Thanks to its intrinsic parallelism, closed-loop IMC (CL-IMC) can ultimately achieve O(1) complexity [4], vastly improving upon the O(n3) complexity of conventional digital systems. CL-IMC is particularly suited to accelerate next-generation communication networks such as the predicted 6G massive multiple-input multiple-output (MIMO) framework. In MIMO, base stations (BS) equipped with antenna arrays communicate with many users at once, performing heavy matrix-based pre- and post-processing operations both in the uplink, where distortion and noise must be removed from received signals, and in the downlink, where transmitted data must be suitably precoded to maximize throughput [5]. We present a novel CL-IMC circuit for massive MIMO acceleration, suitable for both uplink and downlink processing by reconfiguring input/output pairs [6]. The circuit consists of two memory arrays, each mapping the channel matrix H, feedback-connected by means of two arrays of transimpedance amplifiers (TIAs). By proper tuning of the TIAs transconductances, the circuit can be adapted to work in both low and high signal-to-noise ratio (SNR) regimes. Simulation results show floating-point-comparable accuracy with as low as 5-bit memory elements and 60 dB, 100 MHz amplifiers [6]. Benchmark simulations on large-scale systems show energy and area efficiency improvements by 3 orders of magnitude with the same throughput of a digital system [6], making CL-IMC a suitable candidate for data processing in next-generation broadband cellular networks.

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