Proceedings of Materials for Sustainable Development Conference (MAT-SUS) (NFM22)
DOI: https://doi.org/10.29363/nanoge.nfm.2022.002
Publication date: 11th July 2022
This talk is about the challenges and trade-offs in the design of digital scalable neuromorphic processing architectures. We will talk about IMEC's achievements in neuromorphic sensory and event-based processing technologies. We specifically focus on the IMEC RISC-V-based neuromorphic processor (SENeCA) in comparison to the other state-of-the-art architectures.
SENeCA is a RISC-V-based digital neuromorphic processor to accelerate bio-inspired Spiking Neural Networks for extreme edge application (from 1M to 100M neurons) in /near-sensors where ultra-low power and adaptivity features are required. SENeCA is optimized to exploit unstructured spatio-temporal sparsity in computations and data transfer. It improves the available solutions by 1) addressing the flexibility issue in neuromorphic processors, 2) improving the area efficiency by employing a 3-level memory hierarchy, 3) efficient deployment of advanced learning mechanisms and optimization algorithms by accelerating neural operations in three data types: int4, int8 and BrainFloat16 and 4) efficient event communication by using a novel Network-on-Chip with multicasting, compression mechanism and source-based routing.
The last section of the talk will be about "why we think neuromorphic event-based processing is the future of data-driven computing", "why it is not yet on the market" and the "IMEC roadmap to address the main challenges and trade-offs both in software and hardware in the neuromorphic processing domain".
This talk is partially funded and initiated by the Netherlands and European Union’s Horizon 2020 research and innovation projects TEMPO (ECSEL Joint Undertaking under grant agreement No 826655), ANDANTE (ECSEL Joint Undertaking under grant agreement No 876925) and DAIS (Key Digital Technologies Joint Undertaking under grant agreement No 101007273).
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