Resistive Memory Technology for Deep Neural Network Accelerator Hardware
Wooseok Choi a
a SQIT, IBM Research Europe — Zurich
Materials for Sustainable Development Conference (MATSUS)
Proceedings of MATSUS Spring 2025 Conference (MATSUSSpring25)
Advancements in Memristor Technology: From Materials to Devices and Applications - #MemTech
Sevilla, Spain, 2025 March 3rd - 7th
Organizers: Valeria Bragaglia, Wooseok Choi and Juan Bautista Roldan
Oral, Wooseok Choi, presentation 572
DOI: https://doi.org/10.29363/nanoge.matsusspring.2025.572
Publication date: 16th December 2024

In the era of artificial intelligence (AI), the advancement of deep neural network (DNN) algorithms has pushed conventional digital hardware to its limits due to power efficiency constraints [1]. Recently, analog AI hardware, consisting of crossbar arrays of resistive memory devices, has garnered significant attention as a promising solution to overcome the inherent bottleneck of the von Neumann architecture [2]. These systems enable a more efficient mapping of neural network architectures to hardware, with resistive devices representing the weights. Here, resistive memory (ReRAM) technology, in a crossbar array configuration, play a crucial role in realizing analog AI hardware [3]. ReRAM devices store synaptic weights as conductance values, while the crossbar array physically implements the synaptic interconnect on real hardware. Thanks to its design compatibility with the neural network structure, the ReRAM-based crossbar array can accelerate NN inference as well as deep learning through parallel information processing and weight updating within the memory [4]. This presentation introduces conductive-metal-oxide/HfOx ReRAM technology for DNN hardware accelerators and explores the opportunities presented by both the devices and arrays in the system.

memory wall." IEEE Micro (2024).

[2] Jain, Shubham, Hsinyu Tsai, Ching-Tzu Chen, Ramachandran Muralidhar, Irem Boybat, Martin M. Frank, Stanisław Woźniak et al. "A heterogeneous and programmable compute-in-memory accelerator architecture for analog-ai using dense 2-d mesh." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31, no. 1 (2022): 114-127.

[3] Wong, H-S. Philip, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, and Ming-Jinn Tsai. "Metal–oxide RRAM." Proceedings of the IEEE 100, no. 6 (2012): 1951-1970.

[4] Choi, Wooseok, Mamidala Saketh Ram, Donato Francesco Falcone, Tommaso Stecconi, Davide GF Lombardo, Valeria Bragaglia, Antonio La Porta, Folkert Horst, Daniel Jubin, and Bert Jan Offrein. "Nonvolatile Resistive Memory Technology for Deep Neural Network Hardware Applications." Non-Volatile Memory and Selector Devices: Technology and Applications (2025).

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