Proceedings of MATSUS Spring 2025 Conference (MATSUSSpring25)
DOI: https://doi.org/10.29363/nanoge.matsusspring.2025.512
Publication date: 16th December 2024
Memristor devices post-fabricated on top of CMOS circuits promise the avenue to implement low power neuromorphic cores implementing in-memory computing architectures, where the dense memristive matrix act as dense synaptic adaptive memory following bioinspired learning rules as spike-time-dependent-plasticity (STDP). However, the present CMOS-memristive technologies present integration density limitations due to the need of compound MOS-memristor synapses (called 1T1R) as well as problems with control memristive analog values and its variations.
Circuit design techniques can help to overcome this limitations as well as served as an orientation for technological developments to make possible the implementation of advanced low power CMOS-memristive SNN computing architectures.
At IMSE neuromorphic group, we have implemented a dense CMOS-memristive architecture exploiting a CMOL-like geometry to partially overcome the 1T-1R integration limit. Furthermore, we have developed stochastic binary STDP learning rule and experimentally demonstrate its robust performance on a CMOS-memristive hardware. During this talk, the CMOS-memristive SNN computing hardware will be explained, with experimental characterization results at the device and neural system level.
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