Proceedings of MATSUS Spring 2025 Conference (MATSUSSpring25)
DOI: https://doi.org/10.29363/nanoge.matsusspring.2025.098
Publication date: 16th December 2024
In recent years, the cloud-based approach to data classification has been challenged by the edge computing paradigm, which has enabled real-time data processing at the network edge, ideally in close proximity to the sensor that is collecting the data. This paradigm presents significant challenges in terms of power efficiency, compactness, and latency [1, 2]. It is therefore necessary to explore unconventional hardware solutions that are able to meet these exacting requirements.
Brain-inspired architectures, particularly spiking neural networks (SNNs), have the potential to achieve low-latency computation and stateful, energy-efficient operations [3]. However, their current implementations are primarily based on digital or mixed-signal Complementary Metal-Oxide-Semiconductor (CMOS) technologies, which present significant challenges in meeting the demanding memory, area, and power constraints of computing at the network edge. [1].
The integration of emerging memory technologies in the back end of the line (BEOL) of CMOS circuits holds significant promise for enhancing the capabilities of CMOS technology [2, 4] for the development of neuromorphic hardware [5]. The exploitation of their unique properties – including operation voltages compatible with current CMOS technology, as well as analogue, neural-/synaptic-like behaviour – offers an attractive opportunity for realizing energy-efficient and massively parallel computing architectures in conjunction with CMOS technology [3, 5]. Indeed, these features enable efficient computation, neural dynamics, and synaptic plasticity, which are essential traits for emulating the brain's functionality in hardware [4, 6]. However, the achievement of this goal is still an open challenge at several levels, from the fabrication to the integration with circuits to the architecture.
This talk emphasizes the necessity of design-technology co-optimization (DTCO) of emerging memory devices and CMOS circuits to facilitate seamless integration and to leverage the strengths of both technologies. Additionally, it discusses the importance of identifying and addressing issues related to device variability, scalability, and system integration in the co-design of devices, circuits, and algorithms.
This work was supported by the European Research Council (ERC) through the European's Union Horizon Europe Research and Innovation Programme under Grant Agreement No 101042585. Views and opinions expressed are however those of the authors only and do not necessarily reflect those of the European Union or the European Research Council. Neither the European Union nor the granting authority can be held responsible for them. The authors would like to acknowledge the financial support of the CogniGron research center and the Ubbo Emmius Funds (Univ. of Groningen).
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