We fabricate Cu(In,Ga)(S,Se)2 (CIGS) solar cells using the two step-selenization method. First a 500 nm thick 10x multilayer of CuGa/In is sputtered on a soda-lime glass substrate with a Mo back contact layer, followed by evaporation of a 2 µm thick Se layer. This multi-stack is then annealed in a graphite box in a rapid-thermal annealing oven. During the anneal H₂S can be added and removed at different times during the anneal. In a first step we add H₂S in the first phase of the anneal to reduce Ga-diffusion towards the backside of the absorber layer and to include S in the bulk of the absorber layer.  We also add H₂S at the end of the anneal to create a higher band gap S-rich CIGS layer to reduce the front interface recombination. The final absorber layers show a minority carrier recombination time as measured by time resolved photoluminescence measurements of up to 100 ns. The absorber layers are then stored for a few days. Then they are cleaned in an ammonium sulfide solution 1 hour before the CdS top layer is deposited by chemical bath deposition. The solar cells are finished with sputtered ZnO and ITO transparent conductive oxides. The finished solar cells show a best total area efficiency of 16% under AM1.5G illumination. To find out where the major recombination in the devices is located, we performed bias- and temperature-dependent admittance spectroscopy measurements on the cells and compared the results to simulated admittance profiles of CIGS cells [1]. In addition to these devices, the admittance response of devices from Avancis was measured as well.

The results show two distinct recombination patterns, one present at room temperature in forward bias and the second becoming visible in the measurement range only at lower temperatures. The room temperature response showed a bias- and frequency-dependency which in simulations could only be replicated with interface defects. The bias and frequency-dependency of the second recombination response could be replicated with either bulk recombination or a barrier at the CIGS-CdS interface. A clear distinction between the two recombination channels could not be made as these two responses are very similar in the bias voltage versus measurement frequency space. Considering that the series resistance of the devices shows an exponential increase as the temperature is reduced, the barrier at the CIGS-CdS interface seems to be more likely as a cause. The activation energy of the interface defect is of the order of 200 meV, whereas the activation energy of the second recombination response was measured to be about 100 meV deep.

It appears therefore that further improvements to the power conversion efficiency of the devices should involve an improvement of the CIGS-CdS interface properties. This is also in agreement with observations that show that a short anneal at about 200°C after the CdS deposition can improve the fill factor of the devices strongly, likely due to some limited interdiffusion at the interface reducing the recombination behavior at that location.