Proceedings of MATSUS Spring 2024 Conference (MATSUS24)
DOI: https://doi.org/10.29363/nanoge.matsus.2024.021
Publication date: 18th December 2023
Developing high-mobility p-type semiconductors that can be grown using cost-effective scalable methods at low temperatures, has remained challenging in the electronics community for the integration of complementary electronics with the well-developed n-type metal oxide counterparts. Tin (Sn2+) halide perovskites emerge as promising p-type candidates but suffer from low crystallisation controllability and high film defect density, which result in uncompetitive device performance (1). In this talk, I would like to introduce a general overview and recent progress of our group of p-type Sn-based metal halide perovskites for the application of field-effect transistors (FETs). In the first part of the talk, I will mainly address inorganic perovskite thin-film transistors with exceptional performance using high-crystallinity and uniform cesium-tin-triiodide-based semiconducting layers with moderate hole concentrations and superior Hall mobilities, which are enabled by the judicious engineering of film composition and crystallization. The optimized devices exhibit high field-effect hole mobilities of over 50 cm2 V−1 s−1, large current modulation greater than 108, and high operational stability and reproducibility (2). In the second part of the talk, I will introduce A-site cation engineering method to achieve high-performance pure-Sn perovskite thin-film transistors (TFTs). We explore triple A-cations of caesium-formamidinium-phenethylammonium to create high-quality cascaded Sn perovskite channel films, especially with low-defect phase-pure perovskite/dielectric interface. As such, the optimized TFTs show record hole mobilities of over 70 cm2 V−1 s−1 and on/off current ratios of over 108, comparable to the commercial low-temperature polysilicon technique level (3). The p-channel perovskite TFTs also show high processability and compatibility with the n-type metal oxides, enabling the integration of high-gain complementary inverters and rail-to-rail logic gates.
This study was supported by the Ministry of Science and ICT through the National Research Foundation, funded by the Korean government (2021R1A2C3005401, 2020R1A4A1019455, 2020M3F3A2A01085792).
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