Perovskite/silicon tandem solar cells (PSTSC) recently achieved power conversion efficiencies (PCE) exceeding 29% [1, 2]. So far, the highest efficiencies were obtained for tandem solar cells with fully planar wafer front sides and solution-processed perovskite layers. To further increase the performance of PSTSC, it is important to reduce optical losses by implementation of textures on the perovskite subcell and other advanced concepts [3]. In this work, we present PSTSC with tailor-made sinusoidal nanotextures at the perovskite/silicon interface with 750 nm period nm and 300 nm structure height.

The front side of a silicon wafer was nanotextured with a nanoimprint lithography and etching process [4]. The back side of the silicon wafers carried random pyramidal textures. Spin-coated perovskite layers on nanotextured silicon bottom cells feature a planar top surface and adapt perfectly to the sinusoidal texture of the wafer. Importantly, these films tend to form less macroscopic pinholes compared to perovskite layers on planar silicon bottom cells, thus increasing the production yield. The nanostructures reduce reflection losses and in turn lead to a small optical gain in the silicon bottom cell.

To further understand the optical effect of the nanotextured interfaces in PSTSC, optical simulations with the finite element solver JCMsuite were conducted. A detailed sensitivity analysis reveals that a major benefit of the nanostructures is a higher tolerance against variations in thickness of the hydrogenated nano-crystalline silicon oxide (nc-SiO_x:H) layer.

In addition to the optical improvement, we find that the average open-circuit voltage (V_OC) of nanotextured PSTSC increases by approximately 15 mV as also confirmed by photo- (PL) and electroluminescence (EL) measurements. These results indicate that —remarkably— the nanotextures improve not only the optical but also the electronic quality of PSTSC. To further improve light management at the rear side of the silicon bottom cell, we integrated a dielectric buffer layer in combination with screen-printed silver grid fingers into the PSTSC [5]. This back contact design allows to mitigate parasitic absorption losses by reducing the thickness of the transparent conductive oxide (TCO) layer and by diminishing plasmonic losses in the silver back contact. With the combination of both investigated light management measures, we achieved a certified PCE of 29.80% (world record, as of 10 March 2022). We are confident that further finetuning of nanostructures and the dielectric buffer layer will push the PCE of PSTSC well above 30% in the near future.